Issue policy control within a multi-threaded in-order superscalar processor
US9032188B2 · kind B2 · utility
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47Claims
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Key dates
| Filing date | Mar 27, 2008 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Jun 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.