LDMOS with two gate stacks having different work functions for improved breakdown voltage
US9034711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2011 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.