Methods of exposing conductive vias of semiconductor devices and associated structures
US9034752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/927
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.