Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes
US9036400B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Nov 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to integrating a resistive memory device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the CMOS IC device, forming first electrodes over the dielectric layer in a first direction, forming second electrodes over the first electrodes in along a second direction different from the first direction, and forming a two-terminal resistive memory cell at each intersection of the first electrodes and the second electrodes using foundry-compatible processes, including: forming a resistive switching material having a controllable resistance, disposing an interface material including p-doped polycrystalline silicon germanium—containing material between the resistive switching material and the first electrodes, and disposing an active metal material between the resistive switching material and the second electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.