Error correction in a memory device
US9037949B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jul 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.