Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis
US9038006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Apr 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.