Method for planarizing semiconductor devices
US9040315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.