Method for forming solder resist and substrate for package
US9040838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Sep 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1173
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.