Semiconductor device for restraining creep-age phenomenon and fabricating method thereof
US9041172B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.