Memory controller with transaction-queue-monitoring power mode circuitry
US9043633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Nov 18, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.