Error protection for integrated circuits
US9043683B2 · kind B2 · utility
1Cited by
72References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/29
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.