Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
US9047094B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment according to the invention, there is provided a computer processor, the processor comprising: a decode unit for decoding instruction packets fetched from a memory holding a sequence of instruction packets; and first and second processing channels, each channel comprising a plurality of functional units, wherein the first processing channel is capable of performing control operations and comprises a control register file having a relatively narrower bit width, and the second processing channel is capable of performing data processing operations at least one input of which is a vector and comprises a data register file having a relatively wider bit width. The decode unit is operable to detect for each instruction packet whether the instruction packet defines (i) a plurality of control instructions to be executed sequentially on the first processing channel or (ii) a plurality of instructions comprising at least one …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.