Error control in memory storage systems
US9047191B2 · kind B2 · utility
5Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2014 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Jan 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6325
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.