Circuit and method for spin-torque MRAM bit line and source line voltage regulation
US9047965B2 · kind B2 · utility
6Cited by
3References
22Claims
0Family size
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Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The unselected bit lines and source lines are held at the voltage while separately timed signals pull up or pull down the selected bit lines and source lines during read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.