Group word line erase and erase-verify methods for 3D non-volatile memory
US9047973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2014 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | May 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.