Semiconductor structure having a metal gate with side wall spacers
US9048254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | May 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.