Patent · US Active

Semiconductor structure and method of forming a harmonic-effect-suppression structure

US9048285B2 · kind B2 · utility

5Cited by
2References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 1, 2013
Grant dateJun 2, 2015
Priority date—
Expiry dateJul 1, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76898
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.