Processes of making pad-less interconnect for electrical coreless substrate
US9049807B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2008 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Jan 13, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49147
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.