Embedded non-volatile memory
US9054031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jun 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/066
Abstract
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.