Methods for etching dielectric materials in the fabrication of integrated circuits

US9054041B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Johannes von Kluge · Dresden, DE
• Berthold Reimer · Dresden, DE

Key dates

• Filing date: Jul 18, 2013
• Grant date: Jun 9, 2015
• Expiry date: Jul 22, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31155
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.