Inventor · Dresden, DE

Berthold Reimer

15Patents
4h-index
29Co-inventors
52Inventor score

Filing activity: May 24, 2010 → Aug 13, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US8445344B2 Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning Electricity 15 Active
US8247281B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers Electricity 9 Active
US8283232B2 Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing Electricity 6 Active
US10559593B1 Field-effect transistors with a grown silicon-germanium channel Electricity 5 Active
US8815674B1 Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions Electricity 4 Active
US8580133B2 Methods of controlling the etching of silicon nitride relative to silicon dioxide Electricity 3 Active
US8524591B2 Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma Electricity 2 Active
US8703620B2 Methods for PFET fabrication using APM solutions Electricity 1 Active
US8048748B2 Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device Electricity 1 Active
US8658543B2 Methods for pFET fabrication using APM solutions Electricity 1 Active
US8951901B2 Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry Electricity 1 Active
US9054041B2 Methods for etching dielectric materials in the fabrication of integrated circuits Electricity 1 Active
US8357575B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers Electricity 0 Active
US9842762B1 Method of manufacturing a semiconductor wafer having an SOI configuration Electricity 0 Active
US8716136B1 Method of forming a semiconductor structure including a wet etch process for removing silicon nitride Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.