Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures
US9054091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jul 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.