Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
US9054160B2 · kind B2 · utility
10Cited by
54References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2011 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | May 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped openings include an inverse profile which narrows towards a top of the shaped openings. A conductive structure fills the shaped openings wherein the patterned and cured dielectric layer and the permanent antireflective coating each have a conductively filled region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.