Method to form silicide contact in trenches
US9059096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.