Package assembly and method of forming the same
US9059109B2 · kind B2 · utility
12Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/2076
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.