In-situ relaxation for improved CMOS product lifetime
US9059120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2642
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.