Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach
US9059156B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.