Structure and method for making crack stop for 3D integrated circuits
US9059167B2 · kind B2 · utility
7Cited by
23References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.