Method and system for a gallium nitride vertical transistor

US9059199B2 · kind B2 · utility

Assignee

• Avogy, Inc. · US

Inventors

• Hui Nie · Cupertino, US
• Andrew P. Edwards · San Jose, US
• Isik C. Kizilyalli · San Francisco, US
• David P. Bour · Cupertino, US
• Thomas R. Prunty · Santa Clara, US
• Quentin Diduck · Santa Clara, US

Key dates

• Filing date: Jan 7, 2013
• Grant date: Jun 16, 2015
• Expiry date: Jan 7, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/812
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.