Digital PVT compensation for delay chain
US9059716B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Mar 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit-includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements, each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.