Reconfigurable processor and method for processing loop having memory dependency
US9063735B2 · kind B2 · utility
1Cited by
17References
22Claims
0Family size
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Key dates
| Filing date | Oct 13, 2011 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Nov 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.