Method and apparatus for word line suppression
US9064550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2011 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Dec 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.