Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
US9064699B2 · kind B2 · utility
29Cited by
20References
20Claims
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Key dates
| Filing date | Apr 22, 2014 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Apr 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.