Integrated circuit and method of forming integrated circuit
US9064719B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2014 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jul 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48247
Abstract
An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.