Patent · US Active

Breakdown voltage multiplying integration scheme

US9064722B2 · kind B2 · utility

26Cited by

5References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Stephen W. Bedell · Wappingers Falls, US
Bahman Hekmatshoartabari · White Plains, US
Devendra K. Sadana · Pleasantville, US
Ghavam G. Shahidi · Pound Ridge, US
Davood Shahrjerdi · Brooklyn, US

Key dates

Filing date	Mar 13, 2012
Grant date	Jun 23, 2015
Priority date	—
Expiry date	Mar 13, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/111
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.