Methods for minimizing edge peeling in the manufacturing of BSI chips
US9064770B2 · kind B2 · utility
5Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.