Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9064977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.