Reducing store-hit-loads in an out-of-order processor
US9069563B2 · kind B2 · utility
32Cited by
3References
20Claims
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Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.