Negative bitline boost scheme for SRAM write-assist
US9070432B2 · kind B2 · utility
22Cited by
11References
21Claims
0Family size
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Key dates
| Filing date | Nov 12, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Nov 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.