Patent · US Active

Buried digitline (BDL) access device and memory array

US9070584B2 · kind B2 · utility

2Cited by

3References

11Claims

0Family size

Assignee

NANYA TECHNOLOGY CORPORATION · TW

Inventors

Shyam Surthi · Boise, US
Lars Heineck · Dresden, DE

Key dates

Filing date	May 24, 2013
Grant date	Jun 30, 2015
Priority date	—
Expiry date	May 24, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10B12/488
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.