Dynamic error handling using parity and redundant rows
US9075741B2 · kind B2 · utility
3Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jan 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.