Gate stacks and ohmic contacts for SiC devices
US9076651B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.