Template layers for heteroepitaxial deposition of III-nitride semiconductor materials using HVPE processes
US9076666B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 23, 2011 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semi-conductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.