JFET having width defined by trench isolation
US9076760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Apr 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.