Packaging of electronic circuitry
US9076779B1 · kind B1 · utility
0Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jan 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes novel techniques to provide wafer level fan-outs in electronic circuit packages housing one or more circuit devices, at least one of which has input and/or output nodes disposed on opposite facings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.