Residue removal from singulated die sidewall
US9076860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2014 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Apr 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67207
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.