Semiconductor structure with a doped region between two deep trench isolation structures
US9076863B2 · kind B2 · utility
6Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.