Weak keeper circuit for memory device
US9082465B2 · kind B2 · utility
4Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Aug 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.