Patent · US Active

N-well switching circuit

US9082498B2 · kind B2 · utility

3Cited by

4References

19Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Gregory Ameriada Uvieghara · Murrieta, US
Sei Seung Yoon · San Diego, US

Key dates

Filing date	Aug 8, 2013
Grant date	Jul 14, 2015
Priority date	—
Expiry date	Sep 24, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.