Bit line and compare voltage modulation for sensing nonvolatile storage elements
US9082502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Nov 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.